Welcome to the Digital Logic Lab at the University of Jordan! This lab is offered as part of the Computer, Electrical and Mechatronics Engineering curriculum. Through this site, students can gain access to study and extra material; they can also share ideas, help each other and have discussions using site forums. 

Through this lab student will study experiments on basic TTL and CMOS logic gates, including simulations to explore functionality and timing parameters. In addition this lab contains experiments using both simulation and practical hardware implementation on CPLDs or FPGAs, using VHDL for combinational and sequential circuits including multiplexers, demultiplexers, decoders, encoders, shift registers, counters, latches and memory. Experiments in logic design using state machines.